Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell

ABSTRACT

The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type. Specifically, some of the transistors of the ROM cells have their polysilicon layers masked and the ROM cells are then implanted by a first dopant species in the active areas of the exposed transistors. Then the masks are removed from the polysilicon layer, and a second dopant species is implanted in said previously covered layer.

TECHNICAL FIELD

[0001] This invention relates to a method of producing a multi-leveldual-gate ROM type memory in a CMOS process, and to a memory cellstructure produced thereby.

[0002] The invention also relates to a ROM structure, with transistorcells integrated in a semiconductor by a dual gate CMOS process alongwith electrically erasable non-volatile memory cells and low- andhigh-voltage transistors, with all the cells and transistors havingactive areas covered with a layer of gate oxide, in turn overlaid by apolysilicon layer.

BACKGROUND OF THE INVENTION

[0003] As is well known in this specific technical field, there exists agrowing demand from the market, and especially from the smart cardmarket, for integration in a single semiconductor electronic device ofboth ROM (Read Only Memory) circuits and non-volatile, but electricallyerasable, memories such as EEPROMs and/or Flash EEPROMS. Filling thisdemand calls for a significantly more complicated manufacturing processthan a process used to create only a single one of these memories, asthe technologies involved in providing either circuit types are notfully compatible. Accordingly, production costs become higher, andachieving high yield rates is made more difficult. In addition,continuing advances in cryptographic techniques require the use of codesof increasing size, in terms of number of bits, which are not easilydecrypted by reverse engineering methods.

[0004] It is also recognized that an array of ROM cells is essentiallyan array of MOS transistors having conventional source, drain, and gateterminals, and threshold voltages which are set during their fabricationprocess. The threshold is also differentiated such that, for any givenbias of the transistor gate terminal, it becomes possible to determinewhich cells are in the ‘on’ (logic 1) state and which are instead in the‘off’ (logic 0) state by means of a suitable sensing circuit. Tellingwhich cells are in the logic 1 state and which are in the logic 0 stateis usually achieved by implanting or not implanting the source and drainjunctions during the step of implanting these transistor regions.

[0005] This prior approach provides cells with a logic value of 1 and/or0, without a preliminary optical analysis enabling them to be discerned.Other approaches allow the logic value of 1 or 0 to be determined basedon the presence or absence of a transistor.

[0006] There is no current technology available which can provide amulti-level ROM structure, that is, a structure which can store severallogic values in each memory cell.

SUMMARY OF THE INVENTION

[0007] A method of producing a multi-level type of ROM in a CMOS processof the dual-gate type is presented, thereby expanding the informationstorage capacity by means of a readily integratable component with CMOStechnology.

[0008] Embodiments of this invention provide a ROM type of memory cellwhich can store at least three discrete logic levels. Such a cell isobtained by two different dopings of the polysilicon layer that formsthe gate region of the transistor. The step of implanting thesource/drain regions of the transistor which comprises the cell is,therefore, substantially separated from the polysilicon implanting step.

[0009] Based on this concept, a memory device and a method of producingthe multi-level memory of the ROM type in a CMOS process of the dualgate type is presented. First, on a semiconductor substrate, activeareas for transistors including ROM cells, electrically erasablenon-volatile memory cells, and low- and high-voltage transistors arecreated. Oxide and polysilicon layers are deposited over thesemiconductor. The polysilicon layer is masked and etched to definerespective gate regions of the ROM cells, non-volatile cells, and low-and high-voltage transistors. The polysilicon layer of some of thetransistors of the ROM cells is masked and the substrate implanted by adopant in the active areas of the exposed transistors. The mask is thenremoved, and a second dopant species is implanted in the semiconductorin areas previously covered by the mask. Finally, the polysilicon layeris masked and subsequently etched to define the gate regions of the ROMcell transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a layout view of a portion of a semiconductor integratedcircuit which incorporates at least one ROM cell formed in accordancewith embodiments of this invention.

[0011]FIG. 2 is a layout view illustrating the same portion of theintegrated circuit of FIG. 1, during a subsequent step.

[0012]FIG. 3 is a layout view illustrating the same portion of theintegrated circuit of FIGS. 1 and 2 during a further subsequent step.

DETAILED DESCRIPTION

[0013] The process steps and structures described herein below do notreflect a complete process flow for manufacturing integrated circuits.The present invention can be practiced in combination with state-of-arttechniques as currently employed in the manufacture of integratedcircuits. Explanation of well-known steps has been omitted for brevity.

[0014] Referring in particular to FIG. 1, steps of a first embodimentwhich lead to forming multi-level ROM cells in a CMOS process of thedual gate type will now be described.

[0015] In CMOS processes of the latest generation, MOS transistors areusually formed with their gate regions doped with the same dopant typeas the channel region, and it is to this feature that the term “dualgate” applies in technical language. To this aim, it is necessary forthe gate region to be left unprotected during the process step whichprovides heavy source drain implants.

[0016] Advantageously in embodiments of this invention, the memorycircuit that incorporates the ROM cells 1 is integrated in asemiconductor together with a memory circuit of a different typeincorporating electrically erasable non-volatile cells of the EEPROM orFlash EEPROM type. Circuitry is also associated with the matrix ofmemory cells including both low-voltage (LV) MOS transistors andhigh-voltage (HV) MOS transistors.

[0017] The source and drain junctions of low-voltage MOS transistors areusually formed with a gentle profile by a double dopant implantationreferred to as LDD (Lightly Doped Drain) implantation.

[0018] In the integrated memory circuit of embodiments of thisinvention, the HV transistors are needed for handling high (>12 V)voltages during the step of programming the non-volatile memory cells.During the heavy source and drain implanting step applied to the LVtransistors, the HV transistors are wholly masked off. The heavyimplantation is only carried out in contact regions, to ensure goodcontacting.

[0019] Reference will be made to an instance of the memory cells beingN-channel cells, although the same considerations would also apply toP-channel cells once all dopant types are reversed.

[0020] First defined on a semiconductor substrate 10 are the activeareas of the various transistors which comprise the memory circuitsdescribed hereinabove. Thus, both the active areas of the ROM cells 1and the active area of the non-volatile memory cells forming the FlashEEPROM circuit portion are defined. In addition, low- and high-voltageMOS transistors of the circuitry associated with the cell matrix areformed.

[0021] For example, active areas 2 are defined for the transistors ofthe ROM cells, as shown in FIG. 1. Of course, there would be onetransistor for each active area. The active areas 2 are T-shaped. Shownin FIG. 1 are an arbitrary number of adjacent cells, each having arespective active area 2. Grown on top of the active areas 2 is a thinlayer of gate oxide (not shown because conventional). This step impliesoxidation of the whole memory circuitry. At this stage, a layer ofpolysilicon, as required for forming the gate regions of the memory celltransistors, is deposited (not shown because conventional).

[0022] Conventional masking, etching, flushing, and implanting stepsenable definition of the standard low-voltage MOS transistors withsource and drain junctions of the LDD type. These steps lead to thedefinition of the polysilicon layer, and are preliminary to the LDDlight implanting steps, formation of spacers, and heavy source and drainimplantations, also for the LDD transistors.

[0023] However, the gate regions of the ROM cell transistors are definedat a later stage, and so are those of the EEPROM cells and the HVtransistors.

[0024] During the source and drain n+ implanting step for thelow-voltage transistors, certain ROM cells 1, such as those referenced 5in FIG. 2, are masked such that their gate region layer of polysiliconcan be subjected to a subsequent p+ dopant implanting step. This maskingstep essentially allows the logic state of the ROM cell to beprogrammed, and the mask can be regarded here as a program mask.

[0025] The above cells 5 will be exposed when the source and drain p+implantation is to be carried out, whereas the cells previouslyimplanted with the N+ dopant will be covered.

[0026] In essence, one step of the method provides for the polysiliconlayer to be doped with N dopant, and a subsequent step provides for thesame polysilicon layer to be doped with P dopant. During theseimplanting steps, the source and drain regions of the ROM cells 1 wouldbe covered with the polysilicon layer and not implanted.

[0027] Thus, in the processing, two separate different dopings areprovided for the polysilicon layer, which means that the process is adual gate type wherein the gate is doped with the same dopant as thechannel region of the cell. Furthermore, it is important in embodimentsof the invention to have the source/drain implantation separated in timefrom the polysilicon implantation.

[0028] At the end of these process steps, the polysilicon layer of thematrix of ROM cells 1 will be doped in some areas with dopant of the Ntype, and in other areas with dopant of the P type. Accordingly, thepolysilicon layer of the matrix of cells 1 with N-doped gates willexhibit a typical threshold, whereas the cells with P-doped gates willhave a much higher threshold because of the different work function ofthe P-doped polysilicon from the N-doped polysilicon. This enables thefirst two logic levels of the inventive memory structure to be defined.

[0029] With an appropriate masking step and subsequent etching, thepolysilicon layer of the matrix of cells 1 is then defined. By thisetching, the HV transistors of the integrated circuit and the LVtransistors forming the Flash EEPROM cells are also defined.

[0030] Further light source and drain implantations are provided for thematrix of ROM cells 1. During these implantations, a third logic levelcan be obtained by fully covering some cells, which will thus remaindisconnected and carry no current under any bias conditions.

[0031] The result from these steps allows ROM cells to be produced withthree logic levels each, in a dual gate process involving no more masksthan are used in a standard process for making EEPROMs or Flash EEPROMsfor smart cards.

[0032] The array of ROM cells is provided naturally with three logiclevels per cell, which allows the information storage capacity of theROM to be increased exponentially.

[0033] For example, with eight cells, this capacity is raised from2{circumflex over ( )}8=256 codes to 3{circumflex over ( )}8=6,561codes; with sixteen cells, it is raised from 65,536 codes to 43,046,721different codes; etc.

[0034] The ROM cells are produced according to embodiments of theinvention by differentially doping the gates of the correspondingtransistors, also in a dual gate process environment.

[0035] Of course, the memory structure of this invention would requirededicated sensing circuitry for decrypting the logic informationcontained at the three levels of each cell by translating it fromternary to binary logics. However, this represents no significantdisadvantage when the increase in storage capacity is considered. Afurther advantage of this three-level design is that ternary logicswould make it even more difficult to grasp the information stored, orbetter, encrypted, in the memory structure of embodiments of thisinvention.

[0036] Changes can be made to the invention in light of the abovedetailed description. In general, in the following claims, the termsused should not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims, but should beconstrued to include all methods and devices that are in accordance withthe claims. Accordingly, the invention is not limited by the disclosure,but instead its scope is to be determined by the following claims.

1. A method for producing a multi-level memory of the ROM type in a CMOSprocess of the dual gate type, comprising: on a semiconductor substrate,defining respective active areas for transistors of ROM cells,electrically erasable non-volatile memory cells, and low- andhigh-voltage transistors; depositing a layer of gate oxide over saidactive areas; depositing a polysilicon layer over the gate oxide layer;masking, and then etching, the polysilicon layer to define, bysuccessive steps, respective gate regions of a portion of the ROM cells,non-volatile cells, and low- and high-voltage transistors; masking thepolysilicon layer of some of the transistors of the ROM cells, andimplanting a first dopant species in the active areas of the exposedtransistors; removing the mask from the polysilicon layer, andimplanting a second dopant species in said previously covered layer; andmasking and subsequently etching the polysilicon layer to define thegate regions of the remainder of ROM cell transistors.
 2. The method ofclaim 1 wherein during the step of etching away the polysilicon layer todefine the gate regions of the ROM cells, the gate regions of thehigh-voltage transistors are also defined.
 3. The method of claim 1 ,further comprising a light implanting step for the source and drainregions of the transistors of the ROM cells, wherein during thisimplanting some of the cells are fully masked.
 4. A ROM structure havingtransistor cells integrated in a semiconductor by a dual gate CMOSprocess along with electrically erasable non-volatile memory cells andlow- and high-voltage transistors, all cells and transistors havingactive areas covered with a layer of polysilicon, wherein some of thecells have their polysilicon layer doped with a first type of dopant andothers have their polysilicon layer doped with a second type of dopant.5. A method for producing a multi-level ROM type memory comprising:defining active areas on a semiconductor substrate; forming a gate oxidelayer disposed on the semiconductor substrate; forming a polysiliconlayer on the gate oxide layer; etching portions of the polysilicon layerto form respective gates for one or more low-voltage transistors; dopinga plurality of the low-voltage transistors with a first type dopant in afirst concentration to form lightly doped source and drain regions;forming oxide spacers adjacent to the gates of the plurality oflow-voltage transistors; placing a mask over the substrate that covers afirst set of ROM cells, while leaving a second set of ROM cells exposed;doping the plurality of the low-voltage transistors with the first typedopant in a second concentration; placing a second mask over thesubstrate that covers at least some of the second set of ROM cells andthat leaves at least some of the first set of ROM cells exposed; anddoping a second plurality of the low voltage transistors with a secondtype of dopant; defining the polysilicon layer into gates for the ROMcells for high-voltage cells.
 6. The method of claim 5 , furthercomprising: masking a plurality of ROM cells, leaving the other ROMcells exposed; and implanting source and drain regions for the exposedROM cells.
 7. The method of claim 5 further comprising doping the secondplurality of the low-voltage transistors with the second type dopant inthe first concentration to form lightly doped source and drain regions.8. The method of claim 5 wherein the second concentration is greaterthan the first concentration.
 9. The method of claim 5 wherein the firsttype of dopant is N type.
 10. The method of claim 5 wherein the firstand second masks are program masks.
 11. A ROM structure comprising:first ROM memory cells integrated in a semiconductor layer having apolysilicon layer doped with a first type of dopant and having a firstthreshold voltage; second ROM memory cells integrated in thesemiconductor layer having a polysilicon layer doped with a second typeof dopant and having a second threshold voltage; third ROM memory cellsintegrated in the semiconductor layer that are non-operative whencoupled to standard operating voltages for memory cells; electricallyerasable non-volatile memory cells integrated in the semiconductorlayer; low-voltage transistors integrated in the semiconductor layer;and high-voltage transistors integrated in the semiconductor layer. 12.A method of forming a multi-level ROM comprising: forming active areasfor ROM cells, low-voltage transistor cells, high-voltage transistorcells, and non-volatile memory cells in a semiconductor substrate;implanting a heavy implant of a first type dopant into the substrate fora plurality of the low-voltage transistors while covering one or more ofthe active areas for the ROM cells with a first mask; and subsequentlydefining the ROM cells, low-voltage transistor cells and high-voltagetransistor cells.
 13. The method of claim 12 further comprisingimplanting a heavy implant of a second type dopant into the substratefor a second plurality of the low-voltage transistors while covering oneor more of the active areas for the ROM cells with a second mask. 14.The method of claim 12 further comprising, prior to implanting a heavyimplant: doping one or more of the low-voltage transistors with a firsttype dopant in a first concentration to form lightly doped source anddrain regions; and forming oxide spacers adjacent to the gates of theone or more low-voltage transistors.
 15. The method of claim 12 furthercomprising forming oxide and polysilicon layers on the semiconductorsubstrate, wherein it is a portion of the polysilicon layer that iscovered by the first program mask.
 16. The method of claim 12 furthercomprising: forming active areas for non-volatile ROM cells in thesemiconductor substrate; and subsequently defining the non-volatile ROMcells.